1. Field of the Invention
The present invention relates to a clock synchronization circuit to be used for reception processing in a digital wireless communication system.
2. Description of the Related Art
In the digital wireless communication system, a clock synchronization circuit is used to detect information for deciding sampling timing of a received signal from the received signal itself. Typically, the conventional clock synchronization circuit is formed of a circuit including a mixture of an analog circuit and a digital circuit. For example, the conventional clock synchronization circuit has a configuration in which error detection and averaging of sampling timing are conducted by the digital circuit and its result is supplied to a voltage-controlled oscillator (VCO) via digital/analog conversion (D/A) to rationalize the sampling timing. Systems having such a configuration are described in, for example, Japanese Patent Application Laid-Open (JP-A) 2000-349745 and JP-A 2000-049882.